CPU总线仲裁

背景

在Java中查询底层CAS实现时，了解到CPU总线仲裁的概念。Google后找到如下的文章。

what-is-bus-arbitration-explain-any-two-techniques

CPU总线仲裁实现

• The device that is allowed to initiate data transfers on the bus at any given time is called the bus master. In a computer system there may be more than one bus master such as processor, DMA controller etc.
• They share the system bus. When current master relinquishes control of the bus, another bus master can acquire the control of the bus.
• Bus arbitration is the process by which the next device to become the bus master is selected and bus mastership is transferred to it. The selection of bus master is usually done on the priority basis.

There are two approaches to bus arbitration: Centralized and distributed.

Centralized Arbitration

• In centralized bus arbitration, a single bus arbiter performs the required arbitration. The bus arbiter may be the processor or a separate controller connected to the bus.

• There are three different arbitration schemes that use the centralized bus arbitration approach. There schemes are:

  a. Daisy chaining
  b. Polling method
  c. Independent request

Daisy chaining

The system connections for Daisy chaining method are shown in fig below.

• It is simple and cheaper method. All masters make use of the same line for bus request.
• In response to the bus request the controller sends a bus grant if the bus is free.
• The bus grant signal serially propagates through each master until it encounters the first one that is requesting access to the bus. This master blocks the propagation of the bus grant signal, activities the busy line and gains control of the bus.
• Therefore any other requesting module will not receive the grant signal and hence cannot get the bus access.

Polling method

• The system connections for polling method are shown in figure above.
• In this the controller is used to generate the addresses for the master. Number of address line required depends on the number of master connected in the system.
• For example, if there are 8 masters connected in the system, at least three address lines are required.
• In response to the bus request controller generates a sequence of master address. When the requesting master recognizes its address, it activated the busy line ad begins to use the bus.

Independent request

• The figure below shows the system connections for the independent request scheme.
• In this scheme each master has a separate pair of bus request and bus grant lines and each pair has a priority assigned to it.
• The built in priority decoder within the controller selects the highest priority request and asserts the corresponding bus grant signal.

Distributed Arbitration

• In distributed arbitration, all devices participate in the selection of the next bus master.
• In this scheme each device on the bus is assigned a4-bit identification number.
• The number of devices connected on the bus when one or more devices request for the control of bus, they assert the start-arbitration signal and place their 4-bit ID numbers on arbitration lines, ARB0 through ARB3.
• These four arbitration lines are all open-collector. Therefore, more than one device can place their 4-bit ID number to indicate that they need to control of bus. If one device puts 1 on the bus line and another device puts 0 on the same bus line, the bus line status will be 0. Device reads the status of all lines through inverters buffers so device reads bus status 0as logic 1. Scheme the device having highest ID number has highest priority.
• When two or more devices place their ID number on bus lines then it is necessary to identify the highest ID number on bus lines then it is necessary to identify the highest ID number from the status of bus line. Consider that two devices A and B, having ID number 1 and 6, respectively are requesting the use of the bus.
• Device A puts the bit pattern 0001, and device B puts the bit pattern 0110. With this combination the status of bus-line will be 1000; however because of inverter buffers code seen by both devices is 0111.
• Each device compares the code formed on the arbitration line to its own ID, starting from the most significant bit. If it finds the difference at any bit position, it disables its drives at that bit position and for all lower-order bits.
• It does so by placing a 0 at the input of their drive. In our example, device detects a different on line ARB2 and hence it disables its drives on line ARB2, ARB1 and ARB0. This causes the code on the arbitration lines to change to 0110. This means that device B has won the race.
• The decentralized arbitration offers high reliability because operation of the bus is not dependent on any single device.